1. Field of the Invention
The present invention is directed to a method for polysilicon crystalline (PC) line width measurement post etch in undoped-polysilicon process, and more particularly, to a method for in line electrical measurement of a polysilicon (poly) line width dimension post PC etch prior to doping of the poly.
2. Discussion of the Prior Art
Advanced CMOS and MOSFET circuits, such as 0.35 xcexcm and 0.25 xcexcm generation circuits, have increasingly narrow gate sizes, that are formed by etching a polysilicon layer. After etching the polysilicon layer, which is undoped and also referred to as an intrinsic poly layer, the dimension of the remaining gate is measured to ascertain that the remaining polysilicon gate has the desired dimension, such as the desired line width. Measuring the poly gate line width is typically used for controlling the effective channel length, Leff, located in the substrate below the poly gate and along the gate width between the source and drain of the MOSFET.
MOSFETs having a short effective channel length Leff are desirable, since they are smaller and operate at higher and faster frequencies. Short channel lengths also require narrow gate widths. Typically, the length of the channel is approximately the width of the poly gate.
Conventional measurements of channel lengths or poly gate widths have been performed by measuring electrical characteristics of the poly gate after doping thereof. Doping the poly gate is necessary in order to render the poly gate electrically active so that electrical measurements can be performed. From the electrical measurements of the doped poly gate, the quality of the poly layer etch that patterns and forms the poly gate is determined. In particular, the dimension, such as the width, of the patterned poly gate is determined from the electrical measurements of the doped poly gate.
During semiconductor device or MOSFET integrated circuit (IC) fabrication, due to the increasingly small gate dimensions, rapid feedback of the MOSFET poly layer etch that forms the gate, and measurement of the gate line width, are no longer achieved due to the use of undoped polysilicon in 0.5 xcexcm through 0.25 xcexcm generation integrated circuits (ICs), for example. Further, since undoped polysilicon is not a good electrical conductor, it is not possible to electrically determine the width of the polysilicon gate, hence the quality of the polysilicon layer etch that forms the gate, by measuring electrical characteristics of the undoped polysilicon gate.
The inability to rapidly measure polysilicon gate line widths delays electrical characterization of the MOSFET ICs several weeks, where in the meantime, other process steps have been completed. For example, electrical characterization is delayed to post source/drain anneal. This results in a greater risk to the wafer in process for sorting the manufactured MOSFETs according to their operating speed, which is directly related to the channel length or the gate width.
Accordingly, there is a need to provide a method to accurately and rapidly measure electrical characteristics of intrinsic/undoped or lightly doped polysilicon lines to determine line widths thereof.
The object of the present invention is to provide a method of measuring dimensions of a polysilicon (poly) strip formed by etching a poly layer in an undoped or lightly doped polysilicon process that eliminates the problems of conventional measurement methods.
Another object of the present invention is to provide a method of measuring dimensions of the poly strip rapidly and accurately.
Yet another object of the present invention is to provide an early electrical measurement of an intrinsic undoped or lightly doped polysilicon line width post etching an undoped (or lightly doped) poly layer.
A further object of the present invention is to provide a capacitive line width measurement of intrinsic or lightly doped polysilicon.
A still further object of the present invention is to simplify measurement setup of poly line width measurements.
These and other objects of the present invention are achieved by a method of measuring a width of an undoped or lightly doped polysilicon line comprising the steps of:
generating carriers in the polysilicon line with an energy source;
measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and
determining a line width of the polysilicon line from the measured capacitance.
Illustratively, the energy source is a heat or light source. Thus, the carriers in the polysilicon line are generated by heat or exposure to light.
The line width determining step includes measuring a capacitance per unit area associated with the polysilicon line, namely, with the polysilicon line/gate-oxide/substrate structure; and determining a capacitance per unit length of the polysilicon line. The length of the polysilicon line is known by design and is used to approximate a perimeter thereof. Illustratively, the capacitance per unit length determining step includes simulating with a computer model the polysilicon line to determine the capacitance due to edge fringing fields.
The capacitance measurement is performed in accordance to another embodiment of the present invention. In particular, a method of measuring capacitance between a substrate having a dielectric layer formed thereon and a polysilicon formed on the dielectric layer comprises the steps of:
electrically connecting first and second probes to the polysilicon;
electrically connecting a third probe to the substrate;
electrically connecting a first terminal of a capacitance meter to the first probe;
electrically connecting a second terminal of the capacitance meter to the third probe; and
applying a direct current bias across the first and second probes.
A further step includes connecting a capacitor between the first and second probes. The capacitance measuring method further comprises generating carriers in the polysilicon with an energy source. Additional steps include:
electrically connecting a fourth probe to a conductor that supports the substrate; and
electrically connecting the fourth probe to the third probe.
Another embodiment of the present invention includes a method of providing a contact to a substrate, where the contact provides both zero frequency, i.e. direct current (DC), and higher frequency electrical connection to the substrate. This method includes connecting the contact to both the substrate and a conductor that is separated from the substrate by a dielectric layer.